require 'RHDL'

class WashMachine < RHDL::Design
  include RHDL
  def initialize(clk,rst)
    super()
    state_sig = Signal(StateType(:start,:wash,:rinse,:spin,:stop))
    define_behavior {
       process(clk,rst) {
         #async reset:
         if rst == '1'
           puts "RESET"
           state_sig << :start
         elsif clk.event && clk == '1'
           case state_sig.inspect
           when :start
             state_sig << :wash
           when :wash
             state_sig << :rinse
           when :rinse
             state_sig << :spin
           when :spin
             state_sig << :stop
           when :stop
             #stay here till reset
           else
             raise "invalid state! #{state_sig.state}"
           end
         end
       }
       process(state_sig) {
         #prints message whenever state_sig changes:
         puts "Current state is: #{state_sig}"
       }
    }
  end
end

if $0 == __FILE__
  include RHDL
  include TestBench

  clk = ClkGen.generator('0',2,2)
  rst = Signal(Bit.new('1'))
  fsm = WashMachine.new(clk,rst)

  puts "step: 0"
  step
  puts "step: 1"
  step
  puts "step: 2"
  step
  rst << '0'
  18.times do |i|
    puts "step: #{i+2}"
    step
  end
  rst << '1'
  4.times do |i|
    puts "step: #{i+2+18}"
    step
    rst << '0'
  end

end